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Development of a low-voltage DC/DC converter with current control loop.The aim of this work was to develop a voltage converter with an input voltage of up to 5 V, featuring a current control loop. The focus was on designing the control system to reliably handle load transients and changes in input voltage. An important aspect of the control system is the replica current sensing, which must accurately replicate the inductor current to ensure the overall system functions reliably.Led by: Dietmar SpigerTeam:Year: 2025Duration: 15.10.2024 - 15.03.2025
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Investigation of voltage converter combinations.In this bachelor thesis, voltage converters combining switched-capacitor and buck converter stages were investigated. The focus was on analyzing the soft-charging behavior of the combined stages and its impact on reducing losses, increasing power density, and improving efficiency. To validate the simulation results, a discrete demonstrator was developed.Led by: Tim KuhlmannTeam:Year: 2024Duration: 2.6.2024-2.12.2024
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Design of an integrated resonant gate driver using bond-wire inductance for bi-directional gate charge transferThis thesis introduces a fully resonant gate driver operating at 6.82 MHz, utilizing bond-wires as inductance for gate charging. The design optimizes power efficiency by harvesting energy from the gate itself and reusing charge to minimize consumption of the bias capacitor. The system supplies a V_GS of 5V to a silicon MOSFET with a gate capacitance of 1 nF. Simulations estimate a 70% efficiency in charge reuse through resonant back-charging. The study explores the limitations and optimizations of this concept for high-efficiency gate drivers in emerging transistor technologies like GaN.Led by: Saurabh KaleTeam:Year: 2024Duration: 14.04.2024 - 14.11.2024
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Development of a control loop for a DC/DC converter.In this thesis, a discrete current mode control was developed for a 60-V DC/DC converter. The focus of the work was on developing an external control loop that would regulate an integrated DC/DC converter, while also being usable as a standalone system. The objective was to subsequently develop a customized integrated solution based on the discrete control loop.Led by: Dietmar SpigerTeam:Year: 2024Duration: 15.04.2024 - 15.10.2024
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Design of an integrated 400V level shifter with combined passive and active signal transmission.The level shifter presented in this work transfers signals via capacitive coupling from the low-side to the high-side with a reference voltage of up to 400 V. The transmission behavior of RC filters, which are modified by the switching state of a low-side transistor, is utilized. In the resulting combined level shifter, the signal transmission mechanisms of active and passive level shifters complement each other, allowing for the transmission of signals even with higher frequency and amplitude node-switching oscillations. This not only enables an increase in switching frequency but also ensures safer signal transmission. The work was awarded the "Leibniz Talents" prize for outstanding academic achievements.Led by: Christoph HillmerTeam:Year: 2024Duration: 07.02.2024-06.08.2024
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Investigation of memristors for application in neural networks.Artificial neural networks (ANNs) are gaining importance due to advancements in artificial intelligence, as they can analyze complex patterns and operate more energy-efficiently in analog form than traditional computer architectures. Similar to natural neural networks, they consist of neurons that process signals and synapses that weight connections. This weighting is achieved by adjusting the connection properties to enable learning processes. A promising method for realizing artificial synapses is the use of memristors. These components enable efficient and adaptable weighting of connections in ANNs.Led by: Saurabh KaleTeam:Year: 2023Duration: 04.04.2023 - 04.10.2023
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Development of an integrated HV bootstrap circuit.As part of this work, various concepts for a 60 V high-voltage bootstrap supply were investigated. The aim was to develop a fully integrated solution for the high-side bootstrap supply that eliminates the need for external buffer capacitors. This reduces the parasitic impact on the power supply on the chip, saves space on the circuit board, and reduces the number of pads on the chip.Led by: Dietmar SpigerTeam:Year: 2023Duration: 01.12.2022 - 01.06.2023
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Investigation of piezoelectric resonators and development of a measuring circuitThis project explores the use of piezoelectric resonators (PRs) as an alternative to inductors and capacitors for energy storage in power management solutions. Unlike bulky inductors, PRs offer higher energy densities, efficient power conversion, and better integration into ICs due to their planar geometry. They also minimize electromagnetic noise and avoid winding losses at high frequencies. A PCB has been designed to test the application of PRs in a DC-DC Buck-Boost Converter. The study evaluates different PR configurations for their effectiveness in power management systems.Led by: Saurabh KaleTeam:Year: 2023Duration: 30.10.2022 - 30.04.2023
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Concept and Evaluation of a Tool Flow for Emulation-based Analysis of Network-on-Chip ArchitecturesThrough parallelization of hardware processing units the achievable throughput can be increased tremendously. However with emerging multi- and many-core systems traditional communication busses are the limiting factor. An alternative are the so called Network-on-Chip architectures (NoC).Team:Year: 2019Duration: 23.04.2014-13.11.2019
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Implementation of an Automatic Tool for Efficiently Mapping Convolutional Neural Networks to a Vector Processor ArchitectureLed by: Stephan NoltingYear: 2019
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Design of a scalable application-specific architecture for time-domain based SAR imaging autofocusThe quality of synthetic aperture radar (SAR) imaging decreases due to deviations from the ideal flight trajectory. This deviation must be measured very accurately to correct the imaging process. Autofocus procedures can be used to further minimize the residual error. The aim is an architectural concept for executing such an algorithm in hardware.Team:Year: 2018Duration: 19.06.2018-19.12.2018
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Implementation of an Evaluation Framework for Characterizing FPGA-Synthesizable True Random Number GeneratorsNumerous applications rely on random numbers, which are generated by the underlying hardware platforms. Simple (pseudo) random generators are based on iterative functions. In contrast, true random number generators are based on physical processes, which are beyond of predictability. Thus, these kind of architectures can provide random data with high quality. In this thesis, several FPGA synthesizeable random number generators shall be implemented and evaluated.Team:Year: 2018Duration: 19.06.2018-18.12.2018
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Evaluation and Optimization of Application Specific Processor Architectures for Digital Hearing Aids based on Beamforming AlgorithmsIn this thesis, different acoustic beamforming algorithms are to be implemented and evaluated on application-specific processor architectures. The evaluation should include a comparison based on the parameters silicon area, power dissipation and computing power of the various processor architectures.Team:Year: 2018Duration: 06.06.2018-06.12.2018
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Optimization and parallelization of a disparity estimation algorithm for a massive parallel vector processor architecturePorting of the SGM algorithm for stereo camera-based disparity estimation for the VPRO SIMD vector processor architecturte.Team:Year: 2018Duration: 19.10.2017-19.02.2018
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Implementation and Evaluation of a Mobile intelligent EEG-sensor Platform for Brain-computer InterfacesThis thesis deals with the conception and evaluation of a portable platform for recording and real-time classification of EEG data. This includes the implementation of central hardware components into the system, the development of a signal processing framework and the design of a suitable software concept for the generic sequencing of recording and real-time processing of EEG-signals.Team:Year: 2017Duration: 08.05.2017-11.12.2017
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Implementierung und Evaluierung eines generischen Datenpfades für einen VLIW-SIMD HörgeräteprozessorBei Hörgeräteprozessoren kann der Datenpfad an die speziellen Anforderungen der Signalverarbeitungsalgorithmen angepasst werden. Die Breite des Datenpfades kann reduziert werden, um die Leistungsaufnahme zu senken. Andererseits kann die Breite des Datenpfades erhöht werden, um die Leistungsfähigkeit und die Rechengenauigkeit des Hörgeräteprozessors zu erhöhen. In dieser Arbeit soll ein generischer Datenpfad in einem am unserem Institut entwickelten VLIW-SIMD Hörgeräteprozessor implementiert und evaluiert werden, um den Datenpfad optimal und effizient zu nutzen.Team:Year: 2016Duration: 13.06.2016-13.12.2016
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Design and Evaluation of a TTA-based ASIP for the extraction of SIFT FeaturesIn this thesis a transport-triggered architecture (TTA) based processor for the acceleration of computationally intensive image processing algorithms from the field of Advanced Driver Assistance Systems is designed.Team:Year: 2016Duration: 12.05.2016-01.12.2016
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Konzeptionierung, Implementierung und Verifikation eines MAC-Layers für Paket-basierte Powerline KommunikationDer MAC-Layer einer Powerline-basierten Kommunikation übernimmt die Steuerung von Paketen und das Erstellen und Auswerten von Header-Informationen. Zusätzlich werden mehrere CRC-Checksummen überprüft, welche im wesentlichen aus XOR-Matrizen bestehen. Diese sehr heterogene Aufgabenverteilung soll in dieser Arbeit auf einem FPGA umgesetzt werden. Zusätzlich soll die Machbarkeit für die Implementierung auf Softcore-Prozessoren untersucht werden.Team:Year: 2016Duration: 02.05.2017-02.11.2016
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Aufbau und Evaluation eines diskreten analogen Frontends zur OFDM-basierten Powerline-Kommunikation an einer PXIe-EmulationsplattformTo enable communication using a powerline network, digital signals have to be modulated onto analog voltage signals. The implementation of these conversions is carried out by so-called analog front-ends (AFE), which convert the digital signal into an analog version and vice versa. The task of this work is the construction and characterization of two AFEs for use in deep drilling technology. As a result, an evaluation of the signal quality and the physical parameters of influence on the AFEs should be carried out.Team:Year: 2016Duration: 01.05.2016-01.11.2016
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Hardware-related data transmission through SPI with DMA-support für programmable logic devicesIn the context of automation technology, reconfigurable bus systems are used, via which communication takes place between and within manufacturing machinery. On the basis of an exemplary controller, an SPI data transmission with DMA support is realized.Team:Year: 2016Duration: 06.07.2015-15.01.2016
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Evaluation of indoor pathloss models and their suitability for building-specific pathloss predictionThe propagation of radio signals has a determining influence on indoor wireless communication. It can be estimated with the help of pathloss models. However, most of the available models are either not applicable for indoor scenarios or lack accuracy. Subject of this thesis is the analysis of existing models with respect to their suitability for building-specific propagation prediction.Team:Year: 2015Duration: 01.04.2015-01.10.2015
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Conecpt, implementation and evaluation of a fpga based frequency lock for a distributed feedback laserThe wavelength of distributed feedback lasers depends on the laser current and the temperature of the laser diode. Within this thesis an FPGA based frequency lock of a distributed feedback laser will be designed and evaluated. The main work will be the automated frequency determination with the help of rubidium spectroscopy, which is based on pattern matching algorithms.Team:Year: 2015Duration: 30.03.2015-30.06.2015
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Conceptual Design and Implementation of Microbenchmarks for the Analysis of Relevant Multiprocessor CharacteristicsToward an architectural judgement of multiprocessor platforms, in this work, microbenchmarks will be developed in order to extract different isolated hardware parameters.Team:Year: 2015Duration: 09.07.2014-09.01.2015
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Implementation and Evaluation of an FPGA-based ASIP architecture for the extraction of SURF featuresTo accelerate the extraction of SURF features on ASIPs, a customized instruction-set extension has to be developed. In this thesis, it will be evaluated, which speedup can be achieved at which additional FPGA ressources usage.Team:Year: 2015Duration: 19.06.2014-07.01.2015
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Development, Implementation and Evaluation of a wireless sensor circuit for a rotating bioreactorThis thesis deals with the implementation of a specially adapted sensor platform for a rotating bioreactor to grow vessels. This especially demands high requirments on the sensor (temperature, pH, angular position, etc.) and the available area.Team:Year: 2014Duration: 28.05.2014-01.12.2014
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Implementation of Lane Detection on an Application Specific Instruction Set ProcessorFor the evaluation of application-specific extensions of a soft-core processor, an algorithm for detecting driving lanes in camera images will be implemented.Team:Year: 2014Duration: 20.05.2014-20.11.2014
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Implementation and Evaluation of novel Instruction Set Extensions for Pedestrian Detection AlgorithmsFor detecting pedestrians in camera images, novel instruction set extensions for a soft-core processor will be implemented and evaluated.Team:Year: 2014Duration: 20.05.2014-20.11.2014
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Implementation and Evaluation of an FPGA-based heterogenous ASIP Architecture for the Extraction of SIFT FeaturesTo accelerate the extraction of SIFT features on ASIPs, a customized instruction-set extension has to be developed. In this thesis, it will be evaluated, which speedup can be achieved at which processor flexibility for the SIFT feature extraction, processed on an ASIP. The results will be proved by benchmarking results.Team:Year: 2014Duration: 20.05.2014-20.11.2014
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Simulation-based evaluation of the employment of encryption algorithms in the context of low-power wireless communicationThe use of crypto algorithms is essential to enable secure communication via an unsecure channel. With the help of various microcontroller platforms and network simulations the impact of employing encryption algorithms with wireless systems will be analyzed.Year: 2014Duration: 07.05.2014-07.11.2014
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Implementation and Evaluation of a 24-bit Digital Signal Processor Architecture for Hearing Aid DevicesImplementation of an application specific architecture for digital audio signal processing. Evaluation based on a comparison with other architectures in terms of performance, power and area.Team:Year: 2014Duration: 17.03.2014-17.09.2014
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Concept and Implementation of a Digital Sensor Interface for a High Temperature ASIC Demonstration PlatformAs a result of ongoing research on high temperature electronics in drilling applications, an adapted processor architecture has been elaborated. In order to verify the functionality of the design, a demonstration platform is being set up. On that platform, sensor samples can be applied and processed by the proposed architecture. The focus of this work is to provide two kinds of serial interfaces in order to emulate real sensor hardware.Team:Year: 2014Duration: 05.05.2014-05.09.2014
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Implementation and Evaluation of Application Specific Extensions of a Soft-Core Processor for Stereo Signal ProcessingAn algorithm for computing dense disparity maps will be implemented on a soft-core ASIP. Furthermore, application-specific extensions of the processor will be implemented and evaluated.Team:Year: 2014Duration: 01.05.2014-31.08.2014
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Analyse und Verminderung der Fehlerempfindlichkeit einer Hochtemperatur-ProzessorarchitekturElectronics for geothermal drilling tools have to operate reliably at high ambient temperatures without any cooling. Especially in the range from 150 °C up to 300 °C the controllability of integrated transistors drops by orders of magnitude. This increases the possibility of transient errors in the integrated ASIC design. Moreover, rising operating temperatures lead to an accelerated aging of the circuit and increased electro-migration effects. In order to research the fault sensitivity of the drilling tool electronics, in the first step an 8-bit CISC architecture will be evaluated and hardened.Team:Year: 2014Duration: 01.01.2014-31.08.2014
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Implementation and Evaluation of Adaptive Beamforming Algorithms for Hearing Aid SystemsIn this thesis several audio algorithms for directional adaptive filtering of audio signals (so-called beamformer) are implemented for different hardware architectures.Team:Year: 2014Duration: 18.06.2014-29.07.2014
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Construction and implementation of a PC-independent control unit for medical sensorsIn this work, a wireless-connected control unit for controlling chemical sensors for online-monitoring oforganic growth processes in bioreactors is developed and put into operation.Team:Year: 2014Duration: 11.01.2014-11.06.2014
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Implementation of an MMSE-based Noise Reduction Algorithm for Hearing Aid SystemsBased on a reference implementation an MMSE-based noise reduction algorithm should be integrated into the IMS Hearing Aid Matlab Toolbox, a comparison with other available noise reduction algorithms, an evaluation based on different filterbank parameters and a fix-point implementation should be done.Team:Year: 2014Duration: 20.12.2013-22.04.2014
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Implementation and Evaluation of a CNN-Based Scene Labelling Algorithm on a Novel Complex-Addressing Vector Co-Processor ArchitectureThe task of this thesis is to modify the open-source LLVM compiler tool chain to support a novel complex addressing vector co-processor architecture.
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Design and Evaluation of a High Performance Vector Processor Memory Architecture for CNN-Based Scene Labelling AlgorithmsThe task of this thesis is to evaluate the memory structure requirements of a pre-designed CNN algorithm. Based on this profiling, different approaches to increase the performance of the memory system of the VPRO complex-addressing vector processor, designed at the Institute of Microelectronic Systems, shall be designed and evaluated.Team:
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Porting and optimization of a vector processor architecture for the dSPACE MicroAutoBox for scene analysis in the field of driver assistance systemsThe task of this work is to port the vector processor developed at the institute for the dSPACE MicroAutoBox rapid prototyping platform for automotive applications. In addition to setting up the toolchain, the processor shall be optimized for the targeted Xilinx Kintex FPGA.Year: 2019
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Implementation and Evaluation of a Vector-Co-Processor Unit for Efficient Processing of Video-Based Advanced Driver Assistance SystemsBased on previous works, the task of this thesis is to implement an existing instruction set architecture (ISA) for a Xilinx Virtex-6 FPGA ml605 platform. The ISA was generally designed for the field of advanced driver assistance systems, and, in particular, for the efficient computation of scene classification using convolutional neural networks.Team:Year: 2018
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Implementation and Evaluation of an FPGA-based ASIP Architecture for the Extraction of FAST-BRIEF Image FeaturesTo accelerate the extraction of FAST-BRIEF image features on ASIPs, a customized instruction-set extension has to be developed. In this thesis, it will be evaluated, which speedup can be achieved and which additional FPGA ressources are necessary for the acceleration of the algorithm.Team:
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Conception and Implementation of an FPGA-based Architecture for Finding Corresponding Image Features in Images of Stereo Camera SystemsTo find corresponding SIFT-image features in stereo image pairs, different matching algorithms can be applied. In this work, an appropriate matching algorithm for this application has to be identified and implement on an FPGA-based architecture.Team:
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Performance Evaluation of a VLIW-SIMD Signal Processor for Speech Enhancement AlgorithmsA speech enhancement algorithm is implemented and evaluated in this work. The processor architecture evaluated is the VLIW-SIMD signal processor, which is being developed at this institute.Team:Year: 2015Duration: 01.04.2015-
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Implementation and Evaluation of a Speech Recognition Algorithm on a VLIW-SIMD Signal ProcessorA speech recognition algorithm is implemented and evaluated in this work. The processor architecture evaluated is the VLIW-SIMD signal processor, which is being developed at this institute.Team:Year: 2015Duration: 01.04.2015-
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Implementation and testing of a wireless inertial measurement unit using the Bluetooth Low Energy standardBluetooth as a standard is wide-spread among mobile devices. With this thesis its suitability for use in the area of home/building automation will be analyzed.Team:Duration: 22.01.2013-
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Evaluation of Indoor Pathloss Models and their Applicabilty for building-specific Pathloss PredictionWave propagation inside buildings differs strongly from freespace propagation. Within the scope of this thesis common models will be analyzed regarding their accuracy and applicability with the help of measured data.Team:Year: 2013Duration: 22.01.2013-
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Automated Code Generation Automatisierte Generierung von Simulations- und Mikrocontrollercode zur Analyse von NetzwerkprotokollenWith the help of network simulators the dynamic behavior of a wireless network can be predicted. However simulation code always has to be adapted to the platform code and vice versa. Purpose of this thesis is to analyze, how this process can be automated.Year: 2013Duration: 22.01.2013-
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Development of Inline-Profiling Methods Towards an Advanced Analysis of the Runtime Behavior of Parallel Driver Assistance AlgorithmsTo investigate the non-deterministic runtime behavior of parallel programs, existing library interfaces will be used to integrate profiling methods.Team:Year: 2013Duration: 09.12.2013-
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Analysis of possibilities for wireless communication in drilling mudMultiple sensors are use for downhole orientation. Their data have to be evaluated and forwarded to the surface in order to re-adjust the currently installed tool.Team:Year: 2014Duration: 15.04.2014-
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Implementation, verification and evaluation of a measurement module for medical sensor platformsThis work deals with the commissioning of chemical sensors for the online-monitoring of organic growth processes in bioreactors. The focus will be mainly on the temperature and the pH-value.Team:Year: 2013Duration: 20.12.2013-
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Development, Integration and Evaluation of Electrochemical Biosensor Circuits for BioreactorsThis work deals with the commissioning of chemical sensors for the online-monitoring of organic growth processes in bioreactors. The focus will be mainly on the saturated oxygen, glucose-, lactate and the pH-value.Team:
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Simulation and Evaluation of a Wireless Sensor System for Capturing of Drill String Dynamics above GroundDrill processes have to be automated increasingly in order to keep workers away from danger close the borehole To allow for an optiomal control, dynamic behavior of the drillstring has to be captured and forwarded.Team:Year: 2013Duration: 11.12.2013-
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Development of a reference algorithm for a 3D-visualisation of a vascular graft based on ultrasound imagesTo verify a certain quality of a growing vascular graft, the application of ultrasound can be used to take images of the growing tissue. Based on these images, a 3D-model of the vascular graft can be generated. That allows to apply physical simulations on the growing vascular graft.Team:
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Conception and implementation of a hardware-interface for real-time visualization of audio-analysis results via VGAFor the purpose of realtime-visualization of audio-analysis results via a VGA-display a convenient interface has to be defined and implemtend.Team:Year: 2014Duration: 14.04.2014-
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Conception and implementation of a hardware-unit for frequency-analysis of audio-signals for the purpose of realtime-visualizationFor the purpose of realtime-visualization a hardware-unit for frequency-analysis has to be designed and implemented.Year: 2014Duration: 14.03.2014-
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Development and Evaluation of Dedicated Modules for Interactive SoundsynthesisIn the context of this thesis dedicated hardware-modules for interactive real-time sonification of human movements are developed and evaluated. For emulation of the modules the Digilent ZedBoard is used.Team:Year: 2014Duration: 01.03.2014-
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Implementation and Evaluation of Motion Estimation for Driver Assistance Systems on a Multicore Mobile-Prozessor SoCConcerning the platform evaluation of a mobile processor SoC using driver assistance algorithms, a motion estimation (i.e., PPBM) will be implemented, featuring best exploitation of the available hardware resources.Team:Year: 2014Duration: 01.04.2014-
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Design and Evaluation of a High Performance Vector Processor Memory Architecture for CNN-Based Scene Labelling AlgorithmsThe task of this thesis is to evaluate the memory structure requirements of a pre-designed CNN algorithm. Based on this profiling, different approaches to increase the performance of the memory system of the VPRO complex-addressing vector processor, designed at the Institute of Microelectronic Systems, shall be designed and evaluated.Team:Year: 1000
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Development of a Heating Appliance for the Characterization of High Temperature ASICsA suitable heating system is needed in order to determine the properties of a high temperature ASIC containing different adder architectures. It should allow the ASIC to be heated uniformly up to 250° C while keeping the temperature of the printed circuit board (PCB) below 140° C. The main problem is the heat flux through the pins of the ASIC, which will cool the ASIC and heat the PCB. The goal of this thesis is to plan and implement this heating system.Team:
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Implementation and Evaluation of a Parameterizable Convolutional Encoder and Viterbi Decoder in VHDLIn this master/diploma thesis a convolutional encoder and corresponding viterbi decoder will be designed and implemented. Particular attention will be given on a fully parameterizable design at the time of synthesis and the amount of space needed on the FPGA. The outcome of this work will be an efficient implementation including the analysis of all design parameter.Team:
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Implementation and Evaluation of Algorithms for the Extraction of Local Image Features on Extended ASIP ArchitecturesTo accelerate the extraction of local image features on ASIPs, customized instruction-set extensions have to be developed. In this thesis, it will be evaluated, which speedup can be achieved at which processor flexibility for a given algorithm, processed on an ASIP. The results will be proved by benchmarking results and transfered to algorithmic- and processor-specific modelling functions.Year: 2015
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Evaluation of Approximate Arithmetic Units for Stochastic Computing Applications in Horizontal and Vertical SIMD Vector ProcessorsBy relaxing the conventional design constraint of fully precise to approximate arithmetic calculations, it is possible to trade-off accuracy for lower power consumption and higher processing performance. At the Architectures and Systems group of the Institute of Microelectronic Systems, a generic VHDL library of approximate adders and multipliers has been implemented, each introducing its own characteristic in terms of error occurrences and error magnitudes of the approximate arithmetic results, circuit timing and circuit area. In this thesis, the trade-off between computational accuracy, performance and power consumption of approximate horizontal and vertical SIMD vector processors shall be evaluated. For this, algorithmic parts of the SIFT feature extraction application are used as a case study.Team:
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Implementation and Evaluation of a Feature Extraction Computer Vision Algorithm for Horizontal and Vertical SIMD Vector ProcessorsReal-Time Processing of complex Computer Vision algorithm requires high computational performance within a stringent power budget. To meet the necessary Performance-per-Watt constraints, application-specific vector processors may be utilized. In this thesis, processing steps from feature extraction algorithms shall be implemented for vertical and horizontal vector processor architectures by exploiting application- and architecture-inherent data-level parallelism. Furthermore, the evaluation of processing performance and power consumption during application execution is part of this thesis.
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Design of a Miniaturized Integrated >100 V DC-DC Converter for Actuator SystemsThis master's thesis focuses on the integration of DC/DC converters for powering actuators that require high voltages greater than 100 V. The aim is to investigate concepts for minimizing discrete high-voltage components and to select an appropriate converter topology that integrates essential control elements within an IC technology with limited voltage values.Led by: Ferdinand PieperTeam:Year: 2024Duration: 16.09.2024 – 16.03.2025
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Design of a Delay Locked Loop with Extended Frequency RangeIn this work, a delay locked loop (DLL) was developed in an integrated 55 nm process, supporting a particularly wide frequency range.Led by: Ferdinand PieperTeam:Year: 2023Duration: 01.04.2023 – 31.08.2023
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Design and characterization of passive three-dimensional components on additively manufactured printed circuit boards.As part of this work, coils and capacitors of various designs were developed and manufactured using additive manufacturing. The goal was to assess the potential of additive manufacturing for integrating passive components into printed circuit boards and to evaluate their suitability as a compromise solution between fully integrated and discrete components.Led by: Ferdinand PieperTeam:Year: 2023Duration: 15.12.2022 – 15.06.2023
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Measurement and Investigation of Inductance Roll-Off in Integrated Inductors under different DC and AC test conditionsThis work investigated the significance of integrated inductors for highly compact DC-DC converters. The study focused on the impact of high frequencies on reducing the size, weight, and cost of inductors and analyzed saturation effects that limit their power output. Measurements were conducted on the "inductance decrease" with increasing currents, documenting inductance-current diagrams. Additionally, a high-current-capacity bias tee was constructed to understand the influence of AC and DC currents on inductor behavior. The relationship between inductor geometry and design parameters was also examined.Led by: Ferdinand PieperTeam:Year: 2023Duration: 17.10.2022 – 17.04.2023
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Modeling of Inductor Coupling in Multiphase DC-DC ConvertersIn this work, the impact of coupled inductors in multiphase DC-DC converters was investigated. Based on a state-space representation, a simulation model was developed to compare the behavior of various coupling factors within the same system. The analysis focused on the effects on current ripple in each phase, average current, response to load transients, and stability. The model is intended to support the design process by visualizing the effects of different couplings, thereby accelerating the development of suitable multiphase converters with coupled inductors.Led by: Ferdinand PieperTeam:Year: 2024Duration: 15.08.2023 – 15.02.2024
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Design of a 20 A Integrated Inductor Voltage Regulator for Compute Power DeliveryIn this master's thesis, the current challenges and limitations of powering modern processors were analyzed, and possible solutions were developed. A particular focus was on comparing the traditional voltage regulator module (VRM) on the motherboard with integrated voltage regulators (IVR). The study examined how IVRs can enhance performance and reliability by enabling fast load transient responses and a high speed of voltage adaptation.Led by: Ferdinand PieperTeam:Year: 2022Duration: 01.07.2022 – 01.01.2023
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Implementation of a VLIW-MIPS processor for high-temperature applications with compiler supportIn this work, a VLIW variant of an existing MIPS processor shall developed and implemented by adding a second issue slot. To be able to program the architecture using C / C ++, a corresponding compiler support has to be provided. For this, the existing MIPS backend of the open source LLVM compiler shall be adapted and extended.Team:
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Adaptive Regelung von DC-DC-Konvertern unter Einsatz von Machine-Learning-AlgorithmenLed by: Dr.-Ing. Markus OlbrichTeam:Year: 2023Duration: 24.7.2023-24.11.2023
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Implementierung eines FPGA-basierten Systems zur Charakterisierung von SpeicherbausteinenAs part of this work, an FPGA-based test system for memory modules is to be developed in cooperation with hitest.Team:
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Portierung, Kopplung und Optimierung einer generischen Vektorprozessorarchitektur auf ein Xilinx UltraScale+ MPSoC mit eingebettetem ARM ProzessorIm Rahmen dieser Arbeit soll die generische VPRO Vektorprozessorarchitektur auf das Xilinx UltraScale+ MPSoC portiert werden. Dabei soll auf Basis des AXI4 Standard eine Infrastruktur implementiert werden, welche unter anderem einen Speichercontroller sowie Kommunikationsschnittstellen enthält. Die Kopplung des Vektorprozessors mit dem im FPGA verfügbaren ARM Prozessor soll sowohl hardwareseitig über entsprechende Schnittstellen als auch softwareseitig über Treiber und Bibliotheken implementiert werden.Year: 2018Duration: 01.02.2018-
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Implementation and Evaluation of Generic Adder and Multiplier Architectures for Approximate Computing ApplicationsFor adders and multipliers, several architecture modifications towards approximate computing have been proposed in the literature, each introducing its own characteristic in terms of error occurrences and error magnitudes as well as circuit timing, power consumption and required silicon area. Therefore, thorough examinations are necessary to rate the suitability of architectural approximate arithmetic techniques for usage in research projects at the Architectures and Systems Group of the Institute of Microelectronic Systems. The task of this thesis is to implement and evaluate a series of arithmetic adder and multiplier types proposed in publications regarding architectures for approximate computing.
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Implementation and Optimization of a MIPS-Based Soft-Core Processor System for Traffic Sign DetectionEspecially in the automotive sector and in the context of driver assistance systems specialized architectures are used for complex computations that have to work under hard real-time requirements. In particular, the development of so-called soft-core processors for use in field programmable gate arrays (FPGAs) is a subject of current research. By using dedicated extensions of a basic architecture, the processor can be optimized for a specific application or application area. Later reconfigurations of the FPGA allow further adaption of the architecture, making such processor platforms a good exchange between cost, processing power, and efficiency.Team:
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Implementation and Optimization of a MIPS-Based Soft-Core Processor System for a Xilinx Arty-FPGA-BoardThe task of this thesis is to implement and optimize a previously designed MIPS soft-core processor for a low-cost Xilinx Arty FPGA board. The processor shall be included into a multi-clock domain system to make use of the on-board memory and other integrated peripherals.Team:
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Implementation and Evaluation of a Framework for Characterizing Commercial FPGAsBased on previous works, the task of this thesis to characterize several Xilinx Virtex-6 FPGAs for their maximal physical operating frequency. The minimal propagation delay shall be analyzed using oscillators, which are build using the reconfigurable FPGA basic elements.
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Implementation and Evaluation of SIMD and Vector Co-Processors, Tightly Coupled with a MIPS ProcessorThe task of this thesis is to design and implement a vertical and a horizontal vector co-processor for a MIPS-based architecture, developed at the Institute of Microelectronic Systems.
Last Change: 26.03.25
